SPDIF0_CLK_PRED=DIVIDE_1, SPDIF0_CLK_PODF=DIVIDE_1, SPDIF0_CLK_SEL=SPDIF0_CLK_SEL_0, FLEXIO1_CLK_PRED=DIVIDE_1, FLEXIO1_CLK_SEL=FLEXIO1_CLK_SEL_0, FLEXIO1_CLK_PODF=DIVIDE_1
CCM D1 Clock Divider Register
| FLEXIO1_CLK_SEL | Selector for flexio1 clock multiplexer 0 (FLEXIO1_CLK_SEL_0): derive clock from PLL4 1 (FLEXIO1_CLK_SEL_1): derive clock from PLL3 PFD2 2 (FLEXIO1_CLK_SEL_2): derive clock from PLL5 3 (FLEXIO1_CLK_SEL_3): derive clock from pll3_sw_clk |
| FLEXIO1_CLK_PODF | Divider for flexio1 clock podf. Divider should be updated when output clock is gated. 0 (DIVIDE_1): Divide by 1 1 (DIVIDE_2): Divide by 2 2 (DIVIDE_3): Divide by 3 3 (DIVIDE_4): Divide by 4 4 (DIVIDE_5): Divide by 5 5 (DIVIDE_6): Divide by 6 6 (DIVIDE_7): Divide by 7 7 (DIVIDE_8): Divide by 8 |
| FLEXIO1_CLK_PRED | Divider for flexio1 clock pred. Divider should be updated when output clock is gated. 0 (DIVIDE_1): Divide by 1 1 (DIVIDE_2): Divide by 2 2 (DIVIDE_3): Divide by 3 3 (DIVIDE_4): Divide by 4 4 (DIVIDE_5): Divide by 5 5 (DIVIDE_6): Divide by 6 6 (DIVIDE_7): Divide by 7 7 (DIVIDE_8): Divide by 8 |
| SPDIF0_CLK_SEL | Selector for spdif0 clock multiplexer 0 (SPDIF0_CLK_SEL_0): derive clock from PLL4 1 (SPDIF0_CLK_SEL_1): derive clock from PLL3 PFD2 2 (SPDIF0_CLK_SEL_2): derive clock from PLL5 3 (SPDIF0_CLK_SEL_3): derive clock from pll3_sw_clk |
| SPDIF0_CLK_PODF | Divider for spdif0 clock podf. Divider should be updated when output clock is gated. 0 (DIVIDE_1): Divide by 1 1 (DIVIDE_2): Divide by 2 2 (DIVIDE_3): Divide by 3 3 (DIVIDE_4): Divide by 4 4 (DIVIDE_5): Divide by 5 5 (DIVIDE_6): Divide by 6 6 (DIVIDE_7): Divide by 7 7 (DIVIDE_8): Divide by 8 |
| SPDIF0_CLK_PRED | Divider for spdif0 clock pred. Divider should be updated when output clock is gated. 0 (DIVIDE_1): Divide by 1 1 (DIVIDE_2): Divide by 2 2 (DIVIDE_3): Divide by 3 3 (DIVIDE_4): Divide by 4 4 (DIVIDE_5): Divide by 5 5 (DIVIDE_6): Divide by 6 6 (DIVIDE_7): Divide by 7 7 (DIVIDE_8): Divide by 8 |